Lesson about CPU components (registers, buses) and Fetch Execute cycle. Contains elements of component 1.1.1 (a & b) from OCR A-Level Computer Science spec. Lesson has worksheets with answers including exam style questions.
Contains explanations for the registers (MAR, MDR, CIR, PC), buses (Address, Control and Data bus), control unit and ALU. Also the steps to the Fetch Decode execute cycle with detail on the role of the registers in the cycle.
Included is a Powerpoint with notes and tasks, exam question worksheets and a separate Powerpoint task to help aid progress.
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