This resource is designed for use with the CIE A2 Computing course but can be used with any course which covers the use of loaders in an operating system for managing memory locations of running processes.
The intention is to demonstrate why a loader is needed.
Assumed Prior Knowledge
Students should know that a CPU contains the CU, ALU and a number of registers. They should know (or be told during this exercise) that the Program Counter (PC) contains the address in memory of the next instruction to be executed. They should have a basic understanding of the fetch-decode-execute cycle. They should understand what an interrupt is in the context of the fetch-execute cycle. They should have been introduced to process scheduling. It is not necessary for them to know what the registers are (other than the PC) or what their function is in the fetch-execute cycle.
Any feedback welcome.
The intention is to demonstrate why a loader is needed.
Assumed Prior Knowledge
Students should know that a CPU contains the CU, ALU and a number of registers. They should know (or be told during this exercise) that the Program Counter (PC) contains the address in memory of the next instruction to be executed. They should have a basic understanding of the fetch-decode-execute cycle. They should understand what an interrupt is in the context of the fetch-execute cycle. They should have been introduced to process scheduling. It is not necessary for them to know what the registers are (other than the PC) or what their function is in the fetch-execute cycle.
Any feedback welcome.
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